Current integrated circuits such as employed in dynamic random access memories (DRAM) employ multiple layers of metal for interconnection. This requires vertical connections between metal layers. These vertical connections are called vias. These vias are formed in the semiconductor wafers before the wafers are cut into individual integrated circuits.
Vias are formed in etched holes above a prior metal line. The holes are etched using a patterned photoresist layer. A photoresist layer is deposited on the entire surface of the semiconductor wafer. The photoresist layer is selectively exposed to light everywhere a via is to be etched. The light exposed portions of the photoresist layer are developed and then removed leaving a hole over each location where a via is to be formed. The hole serves to enable selective etching of an oxide layer. In order to form a good via all the oxide covering the metal line must be etched away. This process leaves the metal lines exposed where the vias are to be formed.
The next task is the removal of the remaining photoresist layer. In the prior art this is a multistep process that typically employs organic solvent that attacks the photoresist material. Such organic solvents are used when metal lines are exposed. Other processes not related to this invention are used when metal lines are not exposed. The typical organic solvents used are harmful to personnel and hazardous to the environment. Due to the expense of the organic solvent for acquisition, handling and disposal, elimination of any operation using such organic solvents would be advantageous.